1. Field of the Invention
The present invention relates to a charge pump circuit, especially a charge pump circuit having reduced clock feed-through, reduced charge injection and reduced up/down current mismatch.
2. Description of the Prior Art
Phase locked loop (PLL) circuits are utilized in various types of electronic devices and systems. The PLL circuits are typically utilized in devices for clock signal generation, clock sampling, signal synchronization and frequency synthesis for generating clocks and signals. Charge pump circuits are often used for changing voltage levels in PLL circuits.
Please refer to FIG. 1. FIG. 1 shows a prior art charge pump circuit 100. The charge pump circuit 100 includes a charge current mirror 10, a discharge current mirror 20, a p-channel metal-oxide semiconductor (PMOS) switch K5, and an n-channel MOS (NMOS) switch K6. The charge current mirror 10 comprises PMOS transistors K1 and K2, both coupled to a voltage source VDD for providing a charge current Iup. The discharge current mirror 20 comprises NMOS transistors K3 and K4, both coupled to ground for providing a discharge current Idn.
The PMOS switch K5 and the NMOS switch K6 are both coupled to a charge pump output OUT and controlled by control signals UN and DP generated from a phase frequency detector (PFD) 30. However, when the control signals change from HIGH to LOW or from LOW to HIGH, the state transitions may cause an unwanted voltage swing at the charge pump output OUT due to parasitic capacitors Cgsp, Cgdp, Cgsn, and Cgdn coupled to the PMOS switch K5 and the NMOS switch K6. The above voltage swing effect is called clock feed-through.
Besides, when the PMOS switch K5 and NMOS switch K6 are turned off, the charge in the depletion region of the channel will be injected to the parasitic capacitors Cgsp, Cgdp, Cgsn and Cgdn, also causing an unwanted voltage swing at the charge pump output OUT. The above voltage swing effect is called charge injection.
Further, the voltage swing may cause the up/down current mismatch to the charge pump circuit 100. For example, when the voltage level at the charge pump output OUT becomes higher, the drain-to-source voltage of the NMOS transistor K4 will be higher, increasing the current flowing from the charge pump output OUT through the NMOS switch K6. Moreover, when the voltage level at the charge pump output OUT becomes higher, the source-to-drain voltage of the PMOS transistor K2 will become lower, lowering the current flowing from the voltage source VDD through the PMOS transistor K2.
The aforementioned clock feed through, charge injection and up/down current mismatch effect caused by the voltage swing of the charge pump output OUT will result in spurious noise in the output signals generated from the charge pump output OUT, deteriorating the quality of the generated output signals.